1. Field of the Invention
The present invention relates to a counter circuit.
2. Description of the Related Art
Power saving is increasingly demanded for an LSI used for a mobile phone or the like. A method such as clock gating is used to save power for a circuit such as an LSI. Japanese Patent Application Laid-open No. Hei 11-39170 discloses a technology regarding a counter circuit which uses such clock gating.
FIG. 18 illustrates a counter circuit 1 of Japanese Patent Application Laid-open No. Hei 11-39170 where a counter has a 4-bit configuration. As illustrated in FIG. 18, the counter circuit 1 includes a counter unit 10 and a prohibiting gate 40. The counter unit 10 includes flip-flops FF11 to FF14 and an adder 20.
The flip-flops FF11 to FF14 latch 4 bits of input count values count_in[0] to count_in[3] in synchronization with a clock CLK, and output the latched values as output count values count[0] to count[3]. The adder 20 adds “1” to the output count values count[0] to count[3], and inputs the added values as input count values count_in[0] to count_in[3] to the flip-flops FF11 to FF14 again.
The prohibiting gate 40 controls outputting of the clock CLK to a clock input terminal of the flip-flops FF11 to FF14 based on a value of an input enable signal Enable.
However, the circuit such as the counter circuit 1 can only control whether to prohibit input of the clock CLK from the prohibiting gate 40 to the flip-flops FF11 to FF14. Thus, for example, when a value of the enable signal Enable is always “1”, the circuit cannot stop the input of the clock CLK to the flip-flops FF11 to FF14.
In such a counter circuit 1, in the case of processing a count value of a greater number of bits, all the included flip-flops receive the clock CLK to be operated. Thus, for example, the flip-flop that outputs a value of a 4-th bit and the flip-flop that outputs a value of a one-digit higher bit, i.e., 5-th bit, receive the same clock CLK to be operated. In other words, the same clock is supplied to flip-flops greatly different from each other in operation probability between lower and higher digits. As a result, more flip-flops are operated by the clock CLK as a count digit number is greater, causing a problem of an increase in power consumption.